1. Field of the Invention
The present invention relates to a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data and a test apparatus for testing jitter resistance of electronic devices.
2. Related Art
Conventionally, as a circuit for applying jitter into a clock signal, there has been known a jitter applying device that controls a delay of a variable delay circuit for delaying and outputting such clock signal corresponding to jitter to be given. The applicant of the present application has proposed a jitter applying device that controls the delay of the variable delay circuit using shift registers corresponding to jitter to be given as disclosed in Japanese Patent Laid-Open No. 2003-235718 for example. Other applicants have also proposed a jitter applying device using the variable delay circuit as disclosed in Japanese Patent Laid-Open No. 2003-125010 for example.
However, it has been difficult to apply large-amplitude and high-resolution jitter by the conventional jitter applying devices. When the shift resisters are used for the variable delay circuit for instance, a very large number of registers must be used to apply large-amplitude and high-resolution jitter, increasing the circuit scale enormously. The same problem also occurs even when another configuration is used for the variable delay circuit.
Still more, in case of generating an oscillating signal containing a jitter component by superimposing the jitter component to control voltage of a voltage controlled oscillator of a PLL circuit, high-frequency jitter cannot be applied because the control voltage is supplied to the voltage controlled oscillator via a low-pass filter.